Hardware
Chips, memory, interconnects and the machines that run today's workloads.
65 links, newest first.
- HardwareArticle
AAEON PICO-ARU4 pairs Arrow Lake Core Ultra with Pico-ITX
The PICO-ARU4 is a Pico-ITX SBC with an Intel Core Ultra 5 or 7 processor and up to 32GB of soldered LPDDR5. It includes 2.5GbE, display interfaces, USB ports, and M.2 sockets, with Windows and Ubuntu support.
Its compact form factor and range of I/O may suit embedded and mobile systems.
- HardwareArticle
Intel Arc Pro B60 24GB Set for European Launch
The Intel Arc Pro B60 workstation GPU, with 24GB of memory, is expected to launch in Europe in mid to late November, starting at €769.
Its memory capacity and starting price may matter when evaluating workstation GPU options.
- HardwareArticle
Leaked log points to Intel Xe3P variants for discrete GPUs
Wccftech reports that a leaked log indicates Intel Xe3P HPM may power discrete GPUs and also lists an LPM variant, probably for Nova Lake.
The reported variants may offer engineers clues about Intel’s GPU hardware plans.
- HardwareArticle
CamThink NeoEyes NE301 STM32N6 Edge AI Camera
The NeoEyes NE301 is an edge AI camera built around the STM32N6 Arm Cortex-M55 MCU with Neural-ART NPU and a 4MP sensor. It includes 64MB PSRAM, 128MB HyperFlash, Wi-Fi 6 and Bluetooth 5.4.
Its MCU, NPU, memory, and connectivity details may help engineers assess hardware for low-power edge AI deployments.
- HardwareArticle
Intel Nova Lake to Feature a 6th-Generation NPU
A TechPowerUp article reports that Intel’s upcoming Nova Lake desktop processors will use a 6th-generation NPU, one generation ahead of the 5th-generation NPU in Panther Lake. The report cites a Linux patch from Intel engineers.
The NPU generation may help engineers track Intel’s planned on-device AI hardware.
- HardwareArticle
WD Black SN8100 SSD adds an 8TB option
Western Digital’s Black SN8100 SSD is now available in an 8TB version.
The added capacity may matter for engineers who need fast local storage for large workloads.
- HardwareArticle
Leak points to Ryzen 9 9950X3D2 with 192 MB L3 cache
A TechPowerUp report says leaks suggest AMD may launch a 16-core Ryzen 9 9950X3D2 with 192 MB of L3 cache and a 200 W TDP.
The reported cache capacity and power target may interest engineers tracking high-performance desktop CPUs.
- HardwareArticle
Marvell TX9190 Liquid-Cooled CPO Switch at OCP 2025
ServeTheHome reports seeing Marvell’s TX9190 liquid-cooled CPO switch demonstrated at OCP 2025.
The report offers a look at a liquid-cooled CPO switch relevant to engineers following networking hardware.
- HardwareArticle
Banana Pi BPI-R4 Pro adds 10GbE and WiFi 7 options
The BPI-R4 Pro router board uses a MediaTek MT7988A Cortex-A73 SoC with 8GB RAM, two 10GbE SFP+ cages/RJ45 combos, four 2.5GbE ports, and two Gigabit interfaces. It supports OpenWrt, Debian, and Ubuntu.
Its mix of high-speed Ethernet ports and support for several Linux distributions may suit router and networking projects.
- HardwareArticle
Radxa Orion O6N Nano-ITX SBC uses a 12-core CIX P1 SoC
The Radxa Orion O6N is a Nano-ITX single-board computer based on a 12-core CIX P1 SoC, with up to 64GB LPDDR5 and a 30/45 TOPS AI accelerator. It supports Debian and Ubuntu; some Windows drivers are still missing.
Its memory, AI accelerator, storage, and networking options may suit engineers evaluating compact Arm systems.
- HardwarePost on X
SanDisk proposes High Bandwidth Flash for AI memory
The post says SanDisk proposes High Bandwidth Flash (HBF), a NAND-based design targeting 8–16× HBM capacity with similar read bandwidth and price points. First samples are expected in the second half of 2026.
HBF could offer a higher-capacity memory option for AI inference workloads.
- HardwareArticle
Banana Pi BPI-AIM7 RK3588 AI Module
The BPI-AIM7 is an RK3588-based, low-power AI module compatible with the Nvidia Jetson Nano ecosystem.
Engineers evaluating AI hardware can check its compatibility with the Jetson Nano ecosystem.
- HardwareArticle
Maxsun and Abee Announce Workstation with Four Arc Pro B60 GPUs
Maxsun announced a collaboration with Abee on an AI workstation featuring four Intel Arc Pro B60 Dual 48G GPUs, for a total of 192 GB of VRAM.
The configuration is relevant to engineers evaluating GPU memory capacity for AI workloads.
- HardwareRepository
Linux kernel booting chapter updated for modern versions
The fourth chapter of linux-insides on the Linux kernel boot process has been updated to cover modern kernel versions.
Useful for engineers studying how the Linux kernel boots.
- HardwarePost on X
MIT researchers develop a magnetic transistor
MIT researchers reportedly replaced silicon with a magnetic semiconductor to make a transistor. The post says its magnetism improves electrical control and provides built-in memory.
Built-in memory in transistors could simplify circuit design.
- HardwareArticle
Hardware Basics: Cache, Prefetch, False Sharing, and Branches
A light read on hardware basics for programmers, including cache, prefetch, false sharing, and branches.
These topics help engineers understand how hardware behavior can affect software performance.
- HardwarePost on X
Triton’s `tl.make_block_ptr` for GPU data access
A blog post explains how tensors live in memory and covers Triton’s `tl.make_block_ptr`, including striding and offsets, with visuals.
Understanding block pointers can help engineers reason about data access in Triton kernels.
- HardwarePaper
Brook Introduced Stream Computing for GPUs
The 2004 paper “Brook for GPUs: Stream Computing on Graphics Hardware” describes a model in which kernels process elements in streams, offering an alternative to GPU programming through graphics APIs and shaders.
It documents an early stream-and-kernel programming model that helps explain the evolution of GPU computing.
- HardwareArticle
A Reading List on GPU and AI Performance
The post collects performance reads on CUDA matmul optimization, H100 and cuBLAS, LLM inference nondeterminism, transformer inference, scaling, and hardware–model co-design.
It points engineers to material on kernel optimization and performance across AI workloads and hardware.
- HardwarePost on X
Graphcore IPU architecture and parallelism
Graphcore’s Intelligence Processing Unit has 1,472 processor cores, nearly 9,000 parallel threads, and 900 MB of In-Processor Memory. The post says it targets graph-based computation and irregular, sparse workloads.
The core count and on-chip memory architecture are relevant when evaluating accelerators for parallel workloads.
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